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Specification all registers. More...
#include <pcie.h>
Data Fields | |
pciePidReg_t * | pid |
PID. | |
pcieCmdStatusReg_t * | cmdStatus |
Command Status. | |
pcieCfgTransReg_t * | cfgTrans |
Config Transaction. | |
pcieIoBaseReg_t * | ioBase |
IO TLP base. | |
pcieTlpCfgReg_t * | tlpCfg |
TLP Config. | |
pcieRstCmdReg_t * | rstCmd |
Reset Command. | |
pciePmCmdReg_t * | pmCmd |
Power Management Command. | |
pciePmCfgReg_t * | pmCfg |
Power Management Config. | |
pcieActStatusReg_t * | actStatus |
Activity Status. | |
pcieObSizeReg_t * | obSize |
Outbound Translation region size. | |
pcieDiagCtrlReg_t * | diagCtrl |
Diagnostic Control. | |
pcieEndianReg_t * | endian |
Endian Register. | |
pciePriorityReg_t * | priority |
Transaction Priority Register. | |
pcieIrqEOIReg_t * | irqEOI |
End of Interrupt Register. | |
pcieMsiIrqReg_t * | msiIrq |
MSI Interrupt IRQ Register. | |
pcieEpIrqSetReg_t * | epIrqSet |
Endpoint Interrupt Request Set Register. | |
pcieEpIrqClrReg_t * | epIrqClr |
Endpoint Interrupt Request clear Register. | |
pcieEpIrqStatusReg_t * | epIrqStatus |
Endpoint Interrupt status Register. | |
pcieGenPurposeReg_t * | genPurpose [4] |
General Purpose Registers. | |
pcieMsiIrqStatusRawReg_t * | msiIrqStatusRaw [8] |
MSI Raw Interrupt Status Register. | |
pcieMsiIrqStatusReg_t * | msiIrqStatus [8] |
MSI Interrupt Enabled Status Register. | |
pcieMsiIrqEnableSetReg_t * | msiIrqEnableSet [8] |
MSI Interrupt Enable Set Register. | |
pcieMsiIrqEnableClrReg_t * | msiIrqEnableClr [8] |
MSI Interrupt Enable Clear Register. | |
pcieLegacyIrqStatusRawReg_t * | legacyIrqStatusRaw [4] |
Raw Interrupt Status Register. | |
pcieLegacyIrqStatusReg_t * | legacyIrqStatus [4] |
Interrupt Enabled Status Register. | |
pcieLegacyIrqEnableSetReg_t * | legacyIrqEnableSet [4] |
Interrupt Enable Set Register. | |
pcieLegacyIrqEnableClrReg_t * | legacyIrqEnableClr [4] |
Interrupt Enable Clear Register. | |
pcieErrIrqStatusRawReg_t * | errIrqStatusRaw |
Raw Interrupt Status Register. | |
pcieErrIrqStatusReg_t * | errIrqStatus |
Interrupt Enabled Status Register. | |
pcieErrIrqEnableSetReg_t * | errIrqEnableSet |
Interrupt Enable Set Register. | |
pcieErrIrqEnableClrReg_t * | errIrqEnableClr |
Interrupt Enable Clear Register. | |
pciePmRstIrqStatusRawReg_t * | pmRstIrqStatusRaw |
Power Management and Reset Raw Interrupt Status Register. | |
pciePmRstIrqStatusReg_t * | pmRstIrqStatus |
Power Management and Reset Interrupt Enabled Status Register. | |
pciePmRstIrqEnableSetReg_t * | pmRstIrqEnableSet |
Power Management and Reset Interrupt Enable Set Register. | |
pciePmRstIrqEnableClrReg_t * | pmRstIrqEnableClr |
Power Management and Reset Interrupt Enable Clear Register. | |
pcieObOffsetLoReg_t * | obOffsetLo [8] |
Outbound Translation region offset Low. | |
pcieObOffsetHiReg_t * | obOffsetHi [8] |
Outbound Translation region offset High. | |
pcieIbBarReg_t * | ibBar [4] |
Inbound Translation BAR. | |
pcieIbStartLoReg_t * | ibStartLo [4] |
Inbound Translation start Low. | |
pcieIbStartHiReg_t * | ibStartHi [4] |
Inbound Translation start High. | |
pcieIbOffsetReg_t * | ibOffset [4] |
Inbound Translation offset. | |
pciePcsCfg0Reg_t * | pcsCfg0 |
PCS Configuration 0 Register. | |
pciePcsCfg1Reg_t * | pcsCfg1 |
PCS Configuration 1 Register. | |
pciePcsStatusReg_t * | pcsStatus |
PCS Status Register. | |
pcieSerdesCfg0Reg_t * | serdesCfg0 |
SERDES config 0 Register. | |
pcieSerdesCfg1Reg_t * | serdesCfg1 |
SERDES config 1 Register. | |
pcieVndDevIdReg_t * | vndDevId |
Vendor and device ID. | |
pcieStatusCmdReg_t * | statusCmd |
Status Command. | |
pcieRevIdReg_t * | revId |
Class code and Revision ID. | |
pcieBistReg_t * | bist |
Bist Header. | |
pcieType0BarIdx_t * | type0BarIdx |
Type 0 (EP) BAR register. | |
pcieType0Bar32bitIdx_t * | type0Bar32bitIdx |
Type 0 BAR 32bits register. | |
pcieSubIdReg_t * | subId |
Subsystem ID. | |
pcieExpRomReg_t * | expRom |
Expansion ROM base addr. | |
pcieCapPtrReg_t * | capPtr |
Capabilities Pointer. | |
pcieIntPinReg_t * | intPin |
Interrupt Pin. | |
pcieType1BistHeaderReg_t * | type1BistHeader |
Bist Header, Latency Timer, Cache Line. | |
pcieType1BarIdx_t * | type1BarIdx |
Type 1 (RC) BAR register. | |
pcieType1Bar32bitIdx_t * | type1Bar32bitIdx |
Type 1 BAR 32bits register. | |
pcieType1BusNumReg_t * | type1BusNum |
Latency Timer and Bus Number. | |
pcieType1SecStatReg_t * | type1SecStat |
Secondary Status and IO space. | |
pcieType1MemspaceReg_t * | type1Memspace |
Memory Limit. | |
pciePrefMemReg_t * | prefMem |
Prefetch Memory Limit and Base. | |
pciePrefBaseUpperReg_t * | prefBaseUpper |
Prefetch Memory Base Upper. | |
pciePrefLimitUpperReg_t * | prefLimitUpper |
Prefetch Memory Limit Upper. | |
pcieType1IOSpaceReg_t * | type1IOSpace |
IO Base and Limit Upper 16 bits. | |
pcieType1CapPtrReg_t * | type1CapPtr |
Capabilities pointer. | |
pcieType1ExpnsnRomReg_t * | type1ExpnsnRom |
Expansion ROM base addr. | |
pcieType1BridgeIntReg_t * | type1BridgeInt |
Bridge Control and Interrupt Pointer. | |
pciePMCapReg_t * | pmCap |
Power Management Capabilities. | |
pciePMCapCtlStatReg_t * | pmCapCtlStat |
Power Management Control and Status. | |
pcieMsiCapReg_t * | msiCap |
MSI Capabilities. | |
pcieMsiLo32Reg_t * | msiLo32 |
MSI Lower 32 bits. | |
pcieMsiUp32Reg_t * | msiUp32 |
MSI Upper 32 bits. | |
pcieMsiDataReg_t * | msiData |
MSI Data. | |
pciePciesCapReg_t * | pciesCap |
PCI Express Capabilities Register. | |
pcieDeviceCapReg_t * | deviceCap |
Device Capabilities Register. | |
pcieDevStatCtrlReg_t * | devStatCtrl |
Device Status and Control. | |
pcieLinkCapReg_t * | linkCap |
Link Capabilities Register. | |
pcieLinkStatCtrlReg_t * | linkStatCtrl |
Link Status and Control Register. | |
pcieSlotCapReg_t * | slotCap |
Slot Capabilities Register. | |
pcieSlotStatCtrlReg_t * | slotStatCtrl |
Slot Status and Control Register. | |
pcieRootCtrlCapReg_t * | rootCtrlCap |
Root Control and Capabilities Register. | |
pcieRootStatusReg_t * | rootStatus |
Root Status and Control Register. | |
pcieDevCap2Reg_t * | devCap2 |
Device Capabilities 2 Register. | |
pcieDevStatCtrl2Reg_t * | devStatCtrl2 |
Device Status and Control 2 Register. | |
pcieLinkCtrl2Reg_t * | linkCtrl2 |
Link Control 2 Register. | |
pcieExtCapReg_t * | extCap |
Extended Capabilties Header. | |
pcieUncErrReg_t * | uncErr |
Uncorrectable Error Status. | |
pcieUncErrMaskReg_t * | uncErrMask |
Uncorrectable Error Mask. | |
pcieUncErrSvrtyReg_t * | uncErrSvrty |
Uncorrectable Error Severity. | |
pcieCorErrReg_t * | corErr |
Correctable Error Status. | |
pcieCorErrMaskReg_t * | corErrMask |
Correctable Error Mask. | |
pcieAccrReg_t * | accr |
Advanced Capabilities and Control. | |
pcieHdrLogReg_t * | hdrLog [4] |
Header Log Registers. | |
pcieRootErrCmdReg_t * | rootErrCmd |
Root Error Command. | |
pcieRootErrStReg_t * | rootErrSt |
Root Error Status. | |
pcieErrSrcIDReg_t * | errSrcID |
Error Source Identification. | |
pciePlAckTimerReg_t * | plAckTimer |
Ack Latency Time and Replay Timer. | |
pciePlOMsgReg_t * | plOMsg |
Other Message. | |
pciePlForceLinkReg_t * | plForceLink |
Port Force Link. | |
pcieAckFreqReg_t * | ackFreq |
Ack Frequency. | |
pcieLnkCtrlReg_t * | lnkCtrl |
Port Link Control. | |
pcieLaneSkewReg_t * | laneSkew |
Lane Skew. | |
pcieSymNumReg_t * | symNum |
Symbol Number. | |
pcieSymTimerFltMaskReg_t * | symTimerFltMask |
Symbol Timer and Filter Mask. | |
pcieFltMask2Reg_t * | fltMask2 |
Filter Mask 2. | |
pcieDebug0Reg_t * | debug0 |
Debug 0. | |
pcieDebug1Reg_t * | debug1 |
Debug 1 Register. | |
pcieGen2Reg_t * | gen2 |
Gen2. |
Specification all registers.
This structure allows one or more registers to be read or written through a single call.
The user populates one or more pointers to structures. All structures that are non-NULL are read or written.
Once the pointers are populated, use Pcie_readRegs and/or Pcie_writeRegs to perform the actual register accesses