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Specification of the PCS Configuration 1 Register. More...
#include <pcie.h>
Data Fields | |
uint32_t | raw |
[ro] Raw image of register on read; actual value on write | |
uint16_t | pcsErrBit |
[rw] Error bit enable. | |
uint8_t | pcsErrLn |
[rw] Error lane enable | |
uint8_t | pcsErrMode |
[rw] Error injection mode |
Specification of the PCS Configuration 1 Register.
uint16_t pciePcsCfg1Reg_s::pcsErrBit |
[rw] Error bit enable.
Field size: 10 bits
uint8_t pciePcsCfg1Reg_s::pcsErrLn |
[rw] Error lane enable
Field size: 2 bits
uint8_t pciePcsCfg1Reg_s::pcsErrMode |
[rw] Error injection mode
Field size: 2 bits