Data Fields
pcieRegisters_s Struct Reference

Specification all registers. More...

#include <pcie.h>

Data Fields

pciePidReg_tpid
 PID.
pcieCmdStatusReg_tcmdStatus
 Command Status.
pcieCfgTransReg_tcfgTrans
 Config Transaction.
pcieIoBaseReg_tioBase
 IO TLP base.
pcieTlpCfgReg_ttlpCfg
 TLP Config.
pcieRstCmdReg_trstCmd
 Reset Command.
pciePmCmdReg_tpmCmd
 Power Management Command.
pciePmCfgReg_tpmCfg
 Power Management Config.
pcieActStatusReg_tactStatus
 Activity Status.
pcieObSizeReg_tobSize
 Outbound Translation region size.
pcieDiagCtrlReg_tdiagCtrl
 Diagnostic Control.
pcieEndianReg_tendian
 Endian Register.
pciePriorityReg_tpriority
 Transaction Priority Register.
pcieIrqEOIReg_tirqEOI
 End of Interrupt Register.
pcieMsiIrqReg_tmsiIrq
 MSI Interrupt IRQ Register.
pcieEpIrqSetReg_tepIrqSet
 Endpoint Interrupt Request Set Register.
pcieEpIrqClrReg_tepIrqClr
 Endpoint Interrupt Request clear Register.
pcieEpIrqStatusReg_tepIrqStatus
 Endpoint Interrupt status Register.
pcieGenPurposeReg_tgenPurpose [4]
 General Purpose Registers.
pcieMsiIrqStatusRawReg_tmsiIrqStatusRaw [8]
 MSI Raw Interrupt Status Register.
pcieMsiIrqStatusReg_tmsiIrqStatus [8]
 MSI Interrupt Enabled Status Register.
pcieMsiIrqEnableSetReg_tmsiIrqEnableSet [8]
 MSI Interrupt Enable Set Register.
pcieMsiIrqEnableClrReg_tmsiIrqEnableClr [8]
 MSI Interrupt Enable Clear Register.
pcieLegacyIrqStatusRawReg_tlegacyIrqStatusRaw [4]
 Raw Interrupt Status Register.
pcieLegacyIrqStatusReg_tlegacyIrqStatus [4]
 Interrupt Enabled Status Register.
pcieLegacyIrqEnableSetReg_tlegacyIrqEnableSet [4]
 Interrupt Enable Set Register.
pcieLegacyIrqEnableClrReg_tlegacyIrqEnableClr [4]
 Interrupt Enable Clear Register.
pcieErrIrqStatusRawReg_terrIrqStatusRaw
 Raw Interrupt Status Register.
pcieErrIrqStatusReg_terrIrqStatus
 Interrupt Enabled Status Register.
pcieErrIrqEnableSetReg_terrIrqEnableSet
 Interrupt Enable Set Register.
pcieErrIrqEnableClrReg_terrIrqEnableClr
 Interrupt Enable Clear Register.
pciePmRstIrqStatusRawReg_tpmRstIrqStatusRaw
 Power Management and Reset Raw Interrupt Status Register.
pciePmRstIrqStatusReg_tpmRstIrqStatus
 Power Management and Reset Interrupt Enabled Status Register.
pciePmRstIrqEnableSetReg_tpmRstIrqEnableSet
 Power Management and Reset Interrupt Enable Set Register.
pciePmRstIrqEnableClrReg_tpmRstIrqEnableClr
 Power Management and Reset Interrupt Enable Clear Register.
pcieObOffsetLoReg_tobOffsetLo [8]
 Outbound Translation region offset Low.
pcieObOffsetHiReg_tobOffsetHi [8]
 Outbound Translation region offset High.
pcieIbBarReg_tibBar [4]
 Inbound Translation BAR.
pcieIbStartLoReg_tibStartLo [4]
 Inbound Translation start Low.
pcieIbStartHiReg_tibStartHi [4]
 Inbound Translation start High.
pcieIbOffsetReg_tibOffset [4]
 Inbound Translation offset.
pciePcsCfg0Reg_tpcsCfg0
 PCS Configuration 0 Register.
pciePcsCfg1Reg_tpcsCfg1
 PCS Configuration 1 Register.
pciePcsStatusReg_tpcsStatus
 PCS Status Register.
pcieSerdesCfg0Reg_tserdesCfg0
 SERDES config 0 Register.
pcieSerdesCfg1Reg_tserdesCfg1
 SERDES config 1 Register.
pcieVndDevIdReg_tvndDevId
 Vendor and device ID.
pcieStatusCmdReg_tstatusCmd
 Status Command.
pcieRevIdReg_trevId
 Class code and Revision ID.
pcieBistReg_tbist
 Bist Header.
pcieType0BarIdx_ttype0BarIdx
 Type 0 (EP) BAR register.
pcieType0Bar32bitIdx_ttype0Bar32bitIdx
 Type 0 BAR 32bits register.
pcieSubIdReg_tsubId
 Subsystem ID.
pcieExpRomReg_texpRom
 Expansion ROM base addr.
pcieCapPtrReg_tcapPtr
 Capabilities Pointer.
pcieIntPinReg_tintPin
 Interrupt Pin.
pcieType1BistHeaderReg_ttype1BistHeader
 Bist Header, Latency Timer, Cache Line.
pcieType1BarIdx_ttype1BarIdx
 Type 1 (RC) BAR register.
pcieType1Bar32bitIdx_ttype1Bar32bitIdx
 Type 1 BAR 32bits register.
pcieType1BusNumReg_ttype1BusNum
 Latency Timer and Bus Number.
pcieType1SecStatReg_ttype1SecStat
 Secondary Status and IO space.
pcieType1MemspaceReg_ttype1Memspace
 Memory Limit.
pciePrefMemReg_tprefMem
 Prefetch Memory Limit and Base.
pciePrefBaseUpperReg_tprefBaseUpper
 Prefetch Memory Base Upper.
pciePrefLimitUpperReg_tprefLimitUpper
 Prefetch Memory Limit Upper.
pcieType1IOSpaceReg_ttype1IOSpace
 IO Base and Limit Upper 16 bits.
pcieType1CapPtrReg_ttype1CapPtr
 Capabilities pointer.
pcieType1ExpnsnRomReg_ttype1ExpnsnRom
 Expansion ROM base addr.
pcieType1BridgeIntReg_ttype1BridgeInt
 Bridge Control and Interrupt Pointer.
pciePMCapReg_tpmCap
 Power Management Capabilities.
pciePMCapCtlStatReg_tpmCapCtlStat
 Power Management Control and Status.
pcieMsiCapReg_tmsiCap
 MSI Capabilities.
pcieMsiLo32Reg_tmsiLo32
 MSI Lower 32 bits.
pcieMsiUp32Reg_tmsiUp32
 MSI Upper 32 bits.
pcieMsiDataReg_tmsiData
 MSI Data.
pciePciesCapReg_tpciesCap
 PCI Express Capabilities Register.
pcieDeviceCapReg_tdeviceCap
 Device Capabilities Register.
pcieDevStatCtrlReg_tdevStatCtrl
 Device Status and Control.
pcieLinkCapReg_tlinkCap
 Link Capabilities Register.
pcieLinkStatCtrlReg_tlinkStatCtrl
 Link Status and Control Register.
pcieSlotCapReg_tslotCap
 Slot Capabilities Register.
pcieSlotStatCtrlReg_tslotStatCtrl
 Slot Status and Control Register.
pcieRootCtrlCapReg_trootCtrlCap
 Root Control and Capabilities Register.
pcieRootStatusReg_trootStatus
 Root Status and Control Register.
pcieDevCap2Reg_tdevCap2
 Device Capabilities 2 Register.
pcieDevStatCtrl2Reg_tdevStatCtrl2
 Device Status and Control 2 Register.
pcieLinkCtrl2Reg_tlinkCtrl2
 Link Control 2 Register.
pcieExtCapReg_textCap
 Extended Capabilties Header.
pcieUncErrReg_tuncErr
 Uncorrectable Error Status.
pcieUncErrMaskReg_tuncErrMask
 Uncorrectable Error Mask.
pcieUncErrSvrtyReg_tuncErrSvrty
 Uncorrectable Error Severity.
pcieCorErrReg_tcorErr
 Correctable Error Status.
pcieCorErrMaskReg_tcorErrMask
 Correctable Error Mask.
pcieAccrReg_taccr
 Advanced Capabilities and Control.
pcieHdrLogReg_thdrLog [4]
 Header Log Registers.
pcieRootErrCmdReg_trootErrCmd
 Root Error Command.
pcieRootErrStReg_trootErrSt
 Root Error Status.
pcieErrSrcIDReg_terrSrcID
 Error Source Identification.
pciePlAckTimerReg_tplAckTimer
 Ack Latency Time and Replay Timer.
pciePlOMsgReg_tplOMsg
 Other Message.
pciePlForceLinkReg_tplForceLink
 Port Force Link.
pcieAckFreqReg_tackFreq
 Ack Frequency.
pcieLnkCtrlReg_tlnkCtrl
 Port Link Control.
pcieLaneSkewReg_tlaneSkew
 Lane Skew.
pcieSymNumReg_tsymNum
 Symbol Number.
pcieSymTimerFltMaskReg_tsymTimerFltMask
 Symbol Timer and Filter Mask.
pcieFltMask2Reg_tfltMask2
 Filter Mask 2.
pcieDebug0Reg_tdebug0
 Debug 0.
pcieDebug1Reg_tdebug1
 Debug 1 Register.
pcieGen2Reg_tgen2
 Gen2.

Detailed Description

Specification all registers.

This structure allows one or more registers to be read or written through a single call.

The user populates one or more pointers to structures. All structures that are non-NULL are read or written.

Once the pointers are populated, use Pcie_readRegs and/or Pcie_writeRegs to perform the actual register accesses


The documentation for this struct was generated from the following file:

Copyright 2014, Texas Instruments Incorporated