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Specification of the Lane Power Management Control Register. More...
#include <hyplnk.h>
Data Fields | |
uint32_t | raw |
[ro] Raw image of register on read; actual value on write | |
uint8_t | H2L |
[rw] High to Low clocks | |
uint8_t | L2H |
[rw] Low to High clocks | |
uint8_t | PWC |
[rw] Periodic Wakeup Control | |
uint8_t | highSpeed |
[rw] or [ro] High Speed operation is possible | |
uint8_t | quadLane |
[rw] Quad lane enable | |
uint8_t | singleLane |
[rw] Single lane enable | |
uint8_t | zeroLane |
[rw] Zero lane enable |
Specification of the Lane Power Management Control Register.
The Power Management Control Register configures how the HyperLink peripheral dynamically changes the number of lanes to save power.
uint8_t hyplnkLanePwrMgmtReg_s::H2L |
[rw] High to Low clocks
Field size: 3 bits
Number of clocks [in peripheral domain] that the FIFO falls below 1/4 rate before a transition from high speed to low speed is taken.
H2L | Clocks |
---|---|
0 | 64 |
1 | 128 |
2 | 256 |
3 | 512 |
4 | 1024 |
5 | 2048 |
6 | 4096 |
7 | 8192 |
[rw] or [ro] High Speed operation is possible
Field size: 1 bits
It is only settable when using the 45nm SerDes. Otherwise it is a [ro] bit with a value of zero.
uint8_t hyplnkLanePwrMgmtReg_s::L2H |
[rw] Low to High clocks
Field size: 3 bits
Number of clocks [in peripheral domain] that the FIFO is busy before a transition to high speed is taken.
L2H | Clocks |
---|---|
0 | 64 |
1 | 128 |
2 | 256 |
3 | 512 |
4 | 1024 |
5 | 2048 |
6 | 4096 |
7 | 8192 |
uint8_t hyplnkLanePwrMgmtReg_s::PWC |
[rw] Periodic Wakeup Control
Field size: 8 bits
The wakeup period is (PWC + 1) * 65536 SERDES clocks.
The expected value is 94 (10ms).
When the timer expires, the SerDes will be woken up at full speed. If the SerDes is operated at full speed due to other reasons, the timer will start over. That is this controls the maximum interval between full speed events.
uint8_t hyplnkLanePwrMgmtReg_s::quadLane |
uint8_t hyplnkLanePwrMgmtReg_s::zeroLane |
[rw] Zero lane enable
Field size: 1 bits
Setting this bit allows zero lane operation. Zero lane operation shuts down the SERDES.
Clearing this bit prohibits zero lane operation.