![]() |
![]() |
Specification of the Command Status Register. More...
#include <pcie.h>
Data Fields | |
uint32_t | raw |
[ro] Raw image of register on read; actual value on write | |
uint8_t | dbi |
[rw] Set to enable writing to BAR mask registers that are overlaid on BAR registers. | |
uint8_t | appRetryEn |
[rw] Application retry Enable | |
uint8_t | postedWrEn |
[rw] Posted Write Enable | |
uint8_t | ibXltEn |
[rw] Inbound Translation Enable | |
uint8_t | obXltEn |
[rw] Outound Translation Enable | |
uint8_t | ltssmEn |
[rw] Link Training Enable |
Specification of the Command Status Register.
This Register is used to enable address translation, link training and writing to BAR mask registers.
uint8_t pcieCmdStatusReg_s::appRetryEn |
[rw] Application retry Enable
This feature can be used if initialization can take longer than PCIe stipulated time frame.
1 = Enable all incoming PCIe transactions to be returned with a retry response.
Field size: 1 bit
uint8_t pcieCmdStatusReg_s::dbi |
[rw] Set to enable writing to BAR mask registers that are overlaid on BAR registers.
Field size: 1 bit
uint8_t pcieCmdStatusReg_s::ibXltEn |
[rw] Inbound Translation Enable
1 = Enable translation of inbound memory/IO read/write requests into memory read/write requests.
Field size: 1 bit
uint8_t pcieCmdStatusReg_s::ltssmEn |
[rw] Link Training Enable
1 = Enable LTSSM in PCI Express core and link negotiation with link partner will begin.
Field size: 1 bit
uint8_t pcieCmdStatusReg_s::obXltEn |
[rw] Outound Translation Enable
1 = Enable translation of outbound memory read/write requests into memory/IO/configuration read/write requests.
Field size: 1 bit
uint8_t pcieCmdStatusReg_s::postedWrEn |
[rw] Posted Write Enable
Default is 0 with all internal bus master writes defaulting to non-posted.
1 = Enable the internal bus master to use posted write commands.
Field size: 1 bit